Embodiments of the inventive subject matter generally relate to the field of computer architecture, and, more particularly, to a multi-threaded processor having multiple levels of register files.
As processors have evolved, the number of simultaneous threads they support has increased. In order to support this increase, the number of registers in a processor has also increased. This, along with an increase in data word size (e.g., 32 bits to 64 bits) and other factors, has led to larger register sets. As register sets get larger, data access time (latency) and power consumption has also increased.
In an effort to deal with this increase in latency and power consumption, several techniques have been employed, including using mirrored sets of registers that may be accessed independently, and adopting multi-level register files. Multi-level register files provide a smaller register file with lower latency and lower power consumption for primary usage, and a larger register file with higher latency and power consumption for secondary usage.